1. Field of the Invention
The present invention relates to a Liquid Crystal Display (LCD), and more particularly, to a Thin Film Transistor (TFT) array substrate and a method of fabricating the same.
2. Description of Related Art
Generally, a liquid crystal display (LCD) comprises upper and lower substrates opposing each other with liquid crystal interposed there between, and a thin film transistor (TFT) addressing the voltage to the liquid crystal. On the lower substrate, a plurality of gate lines extending in one direction and a plurality of data lines extending in perpendicular direction to the gate lines are formed. In this matrix arrangement, a plurality of TFTs are disposed near the crossover points of the data and gate lines.
Nowadays, the liquid crystal display (LCD) is used for a portable computer such as a laptop computer and is becoming large from the beginning of simple display devices to large size display. The large-sized LCD employs an active matrix array substrate including numerous pixel regions, data and gate lines crossed each other to define the pixel regions, and TFTs (switching device) positioned near the crossover points of the data and gate lines.
In this active matrix type liquid crystal display, a high picture quality and a high definition are current important problems. For this purpose, a method of providing a storage capacitor in parallel with a pixel electrode has been known.
In general, without the storage capacitor, the electric charges of the first signal applied through the TFT for switching the liquid crystal will leak out in a short time after applying the first signal. Therefore, before applying the second signal, the capacitor in parallel with the pixel electrode should be provided to keep up the first electric charges.
In general, for the capacitor the gate line acts as one capacitor electrode and the pixel electrode acts as the other capacitor electrode.
FIG. 1 is a partially enlarged plan view illustrating the array substrate of a conventional active matrix type LCD having a pixel region xe2x80x9cPxe2x80x9d, a storage capacitor xe2x80x9cCxe2x80x9d, a TFT xe2x80x9cAxe2x80x9d and the gate and data lines 35 and 49. A drain electrode 47 of the TFT xe2x80x9cAxe2x80x9d is connected to a pixel electrode 40 of the pixel region xe2x80x9cPxe2x80x9d via a contact hole 57.
A semiconductor channel region 53 is formed between source and drain electrodes 45 and 47 by exposing the portion of the intrinsic semiconductor layer 39. Ohmic contact regions are formed between the intrinsic semiconductor layer 39 and the source and drain electrodes 45 and 47. And gate and data pads (not shown) are formed at one end of the gate and data lines 35 and 49.
FIGS. 2a to 2f cross-sectional views taken along line Ixe2x80x94I of FIG. 1, illustrating process steps of fabricating a TFT array substrate using a conventional four-mask process.
Referring to FIG. 2a, a first metallic layer (not shown) is formed on a substrate 31 and is patterned using a first mask process to form the gate pad (not shown), gate electrode 33 and gate line 36. The first metallic layer is made of a metallic material having a low resistance, such as Aluminum (Al) or Al-alloy. When the gate line is used for the capacitor electrode, the time constant of the gate line increases. Thus, the material having the low resistance such as Aluminum is preferably used for the gate line. This means that Aluminum can decrease the time constant compared with the material having a high resistance such as Tantalum (Ta) or Chrome (Cr).
The gate electrode 33 extended from the gate line 36 is formed at the corner of the pixel region. Referring back to FIG. 1, a portion of the gate line 36 is used for a capacitor electrode of the storage capacitor xe2x80x9cCxe2x80x9d.
As shown in FIG. 2b, a first insulation layer 37 is formed by depositing an inorganic substance such as Silicon Nitride (SiNx) and Silicon Oxide (SiO2) or an organic substance such as BCB (Benzocyclobutene) and acryl on the substrate 31 while covering the gate electrode 33 and the gate line or capacitor electrode 36. Then intrinsic semiconductor layer 39, such as pure amorphous silicon, is formed on the first insulation layer 37. Then extrinsic semiconductor layer 41, such as impurity (n+ or p+) doped amorphous silicon, is sequentially formed on the intrinsic semiconductor layer 39. Then a second metallic layer 43 made of a material such as Molybdenum (Mo), Tantalum (Ta), Tungsten (W), Antimony (Sb) and the like is formed on the extrinsic semiconductor layer 41.
Referring to FIG. 2c, the source and drain electrodes 45 and 47, data line 49 (see FIG. 1), data pad (not shown) and second capacitor electrode 51 having an island shape are formed by patterning the second metallic layer 43 and extrinsic semiconductor layer 41 using a second mask process. The source and drain electrodes 45 and 47 are spaced apart from each other to expose the semiconductor channel region 53. At this time, the extrinsic semiconductor layer 41 is removed using the source and drain electrodes 45 and 47 as a mask. Moreover, carefulness is needed, in this etching step, not to pattern the intrinsic semiconductor layer 39.
The portions of the extrinsic semiconductor layer 41, between the intrinsic semiconductor layer 39 and the source and drain electrodes 45 and 47, act as ohmic contact layers 43a and 43b, respectively.
As shown in FIG. 2d, a second insulation layer or protection layer 53 is formed on the metallic layers 45, 47 and 51 and intrinsic semiconductor layer 39.
Referring to FIG. 2e, the contact holes 55 and 57 are formed by patterning the protection layer 53. Simultaneously, the pixel region xe2x80x9cPxe2x80x9d are formed by patterning the protection layer 53, intrinsic semiconductor layer 39 and first insulation layer 37 using a third mask process except the region for the storage capacitor and the data line.
Referring to FIG. 2f, a transparent conductive substance such as ITO (indium-tin-oxide) is deposited and patterned using a fourth mask process. Thus, the pixel electrode 40, electrically connecting to the second capacitor electrode 51 and drain electrode 47 via contact holes 51 and 57, is formed.
FIG. 3a is an enlarged view illustrating the portion xe2x80x9cCxe2x80x9d of FIG. 2f and FIG. 3b is an equivalent circuit view of FIG. 3a. 
As shown in FIGS. 3a and 3b, the storage capacitor xe2x80x9cCxe2x80x9d includes the first capacitor electrode or the gate line 36. It also includes the second capacitor electrode 51 (having a contact with the pixel electrode 40), first insulation layer 37 (which stores the electric charge as a dielectric layer) and semiconductor layer 42 (the intrinsic and extrinsic semiconductor layers 39 and 41 as a dielectric layer).
According to the conventional method for manufacturing the TFT array substrate using the four-mask process, the process steps are decreased. However, the storage capacitance is also decreased compared to that of the array substrate manufactured using the five-mask process. For better description, the storage capacitance is represented by the following equation:                               C          st                =                              ϵ            ·            A                    d                                    (        1        )            
In the above equation (1), where xe2x80x9cCstxe2x80x9d denotes capacity, xe2x80x9cxcex5xe2x80x9d denotes a dielectric constant, xe2x80x9cdxe2x80x9d represents the thickness of the dielectric layer and xe2x80x9cAxe2x80x9d represents the area of the capacitor electrode. As described in the Equation (1), the storage capacitance xe2x80x9cCstxe2x80x9d is in proportion to the amount of the area xe2x80x9cAxe2x80x9d and is in inverse proportion to the thickness xe2x80x9cdxe2x80x9d of the dielectric layer.
Therefore, due to the fact that the dielectric layer includes two layers (the first insulation layer 37 and semiconductor layer 42) between the two capacitor electrodes 36 and 51, in the conventional four-mask process, the capacitance is decreased.
In order to overcome the problems described above, a preferred embodiment of the present invention provides a method of fabricating a TFT array substrate having a large storage capacitance using the four-mask process for use in an LCD device, which has the high picture quality and high definition.
In order to achieve the above objects, in one aspect, the preferred embodiment of the present invention provides a thin film transistor (TFT) array substrate, including: a substrate; a plurality of a gate lines on the substrate; a plurality of data lines crossing over the gate lines and formed over the substrate; a pixel electrode in a pixel region that is defined by crossing the data and gate lines; a TFT connecting to the pixel electrode; and a storage capacitor connecting to the pixel electrode, said storage capacitor including: the gate line on the substrate; a first insulation layer on the gate line; intrinsic and extrinsic semiconductor layers formed sequentially on the first insulation layer; a first capacitor electrode on the semiconductor layer; a second insulation layer over the first capacitor electrode and semiconductor layer; and a second capacitor electrode on the second insulation layer in a position of corresponding to the first capacitor electrode.
The TFT array substrate has a gate contact hole exposing the portion of the gate line and positioned at the one side of the first capacitor electrode. The TFT array substrate has at least one gate contact hole, and the contact hole penetrates the central part of the first capacitor electrode. The TFT array substrate includes the gate line and first capacitor electrode having electrical connection each other using a transparent conductive electrode.
In order to achieve the above object, in another aspect, the present invention provides a method of fabricating a thin film transistor (TFT) array substrate, including: providing a substrate; depositing a first metallic layer on the substrate; forming a gate electrode and gate line on the substrate by patterning the first metallic layer using a first mask process; forming a first insulation layer over the gate electrode, gate line and substrate; forming an intrinsic semiconductor layer on the first insulation layer; forming an extrinsic semiconductor layer on the intrinsic semiconductor layer; depositing a second metallic layer on the extrinsic semiconductor layer; forming a data line, source and drain electrodes and a first capacitor electrode having an island shape over the gate line by patterning the second metallic layer and extrinsic semiconductor layer using a second mask process; forming a second insulation layer over the data line, source and drain electrodes and first capacitor electrode; forming a drain contact hole by patterning the second insulation layer using a third mask process, simultaneously, forming a pixel region and gate contact hole by patterning the first and second insulation layers and intrinsic semiconductor layer, simultaneously, exposing the portion of the first capacitor electrode by patterning the second insulation layer; depositing a transparent conductive electrode over the entire surface; and patterning the transparent conductive electrode by using a fourth mask process to form an electrode connecting layer connecting the first capacitor electrode with the gate line, to form a pixel electrode connected to the drain electrode via the drain contact hole, and to form a second capacitor electrode extended from the pixel electrode, overlapping the first capacitor electrode and spaced apart from the electrode connecting layer.
In the method of fabricating the TFT array substrate, the gate electrode is made of Aluminum (Al) or Al-alloy. The method of fabricating the TFT array substrate further comprises the step of forming the gate contact hole exposing the portion of gate line and positioned at the one side of the first capacitor electrode by patterning the intrinsic semiconductor layer and first insulation layer. The method fabricates at least one gate contact hole. The contact holes penetrate the central part of the first capacitor electrode and are formed over the gate electrode spaced apart each other. The method further comprises the steps of fabricating a storage capacitor wherein including the second capacitor electrode formed on the second insulation layer over the first capacitor electrode.